Semiconductor manufacturing processes involve the formation and deposition of various layers. Two layers that exist in semiconductor substrate devices are a poly-silicon layer and a substrate layer. Parasitic capacitance exists between such layers, and it is particularly important to control the parasitic capacitance that exists between the poly-silicon layer and layers beneath the poly-silicon layer, including the substrate. In particular for the substrate, conventional poly-to-substrate capacitance can be high, especially for high impedance poly-silicon devices (or “poly-devices”). The poly-silicon layer can be used to form a poly-resistor or a poly-diode.
FIG. 1 shows an example cross section of a semiconductor substrate with a poly-silicon device according to the prior art. A system 100 includes a p-doped substrate 102 with an N-well (“NW”) doped region 104 under a shallow trench isolation (“STI”) dielectric layer 108. A poly-silicon layer (not shown), such as in device 110, on the STI layer 108 can have a capacitance to the N-well doped region 104 represented by capacitance 120. The capacitance 120 can be about 0.1 fF per micron squared when the STI layer 108 has a depth of 0.3 to 0.4 microns. Also shown in FIG. 1 are P-well (PWELL) doped regions 106A and 106B.
One conventional technique for reducing the poly-to-substrate capacitance 120 is to increase the thickness of the STI layer 108. However, increasing the thickness of the STI layer 108 limits the density of devices 110 and also increases cost of the end products.
Shortcomings mentioned here are only representative and are included simply to highlight that a need exists for improved electrical components, particularly for poly-silicon devices employed in consumer-level devices, such as mobile phones. Embodiments described herein address certain shortcomings but not necessarily each and every one described here or known in the art.